Electrostatic discharge (ESD) is one of main factors that cause electrical overstress (EOS) damage to many electronic components. For protecting the electronic components from electrostatic damage, the integrated circuit (IC) is usually equipped with an electrostatic discharge protection circuit for providing an ESD current path. The sudden ESD current is conducted via the ESD current path and blocked from flowing into the integrated circuit in order to protect the integrated circuit.
Generally, the electrostatic discharge current is conducted to the internal portion of the integrated circuit through its pins. For protecting the functional circuits within the integrated circuit, the electrostatic discharge protection circuit is usually arranged beside input/output bonding pads to bypass the ESD current nearby. In views of electrostatic discharge protection, it is necessary to install ESD conducting paths between an input pad, an output pad, a voltage source and a ground terminal.
FIG. 1 schematically illustrates a full-chip protection configuration for protecting a functional circuit within an integrated circuit. As shown in FIG. 1, a plurality of electrostatic discharge protection circuits are connected between the voltage source, the ground terminal, the input/output pads and the functional circuit 11.
A first node N1 is set between the input pad 12 and the functional circuit 11. For preventing generation of the ESD current at the input pad 12, the first node N1 is connected to a voltage source Vdd and a ground terminal Vss through a first electrostatic discharge protection circuit 101 and a second electrostatic discharge protection circuit 102, respectively. By the first electrostatic discharge protection circuit 101, the ESD current between the input pad 12 and the voltage source Vdd fails to flow to the functional circuit 11. By the second electrostatic discharge protection circuit 102, the ESD current between the input pad 12 and the ground terminal Vss fails to flow to the functional circuit 11.
Similarly, a second node N2 is set between the output pad 13 and the functional circuit 11. For preventing generation of the ESD current at the output pad 13, the second node N2 is connected to the voltage source Vdd and the ground terminal Vss through a third electrostatic discharge protection circuit 103 and a fourth electrostatic discharge protection circuit 104, respectively. By the third electrostatic discharge protection circuit 103, the ESD current between the output pad 13 and the voltage source Vdd fails to flow to the functional circuit 11. By the fourth electrostatic discharge protection circuit 104, the ESD current between the output pad 13 and the ground terminal Vss fails to flow to the functional circuit 11.
Since the electrostatic discharge is possibly generated at the region between the voltage source Vdd and the ground terminal Vss, a fifth electrostatic discharge protection circuit 105 is further provided between the voltage source Vdd and the ground terminal Vss. Depending on the flowing directions of the ESD current, the design of the fifth electrostatic discharge protection circuit 105 is variable. The present invention is directed to the electrostatic discharge protection circuit 105 between the voltage source Vdd and the ground terminal Vss.
FIG. 2 is a schematic functional block diagram illustrating the fifth electrostatic discharge protection circuit as shown in FIG. 1. In FIG. 2, the electrostatic discharge protection circuit 20 includes two sub-circuits, i.e. an electrostatic discharge detection circuit 207 and an electrostatic discharge clamp circuit 208. These two sub-circuits are electrically connected between the voltage source Vdd and the ground terminal Vss.
The electrostatic discharge detection circuit 207 is used for sensing whether the electrostatic discharge Sesd is generated. Once the electrostatic discharge Sesd is sensed, a corresponding signal is outputted from the electrostatic discharge detection circuit 207 to the electrostatic discharge clamp circuit 208. That is, the electrostatic discharge detection circuit 207 is used for only detecting the electrostatic discharge without conducting the ESD current. Whereas, in a case that the electrostatic discharge occurs, the electrostatic discharge clamp circuit 208 is triggered by the electrostatic discharge detection circuit 207. Consequently, the ESD current is conducted by the electrostatic discharge clamp circuit 208 while keeping away from the functional circuit 11 inside the integrated circuit chip.
FIG. 3 is plot illustrating the current-voltage relationship of a conventional electrostatic discharge clamp circuit. Generally, the parameters indicating the characteristics of the electrostatic discharge clamp circuit include a trigger voltage Vt, a holding voltage Vh and a second-breakdown current It2.
The trigger voltage Vt of the electrostatic discharge clamp circuit 208 denotes the voltage that enables the electrostatic discharge clamp circuit 208. Moreover, the trigger voltage Vt of the electrostatic discharge clamp circuit 208 is relevant to the speed of conducting the ESD current. For designing the electrostatic discharge clamp circuit 208, the trigger voltage Vt of the electrostatic discharge clamp circuit 208 should be lower than the trigger voltage Vt of the functional circuit.
Once the electrostatic discharge occurs, the electrostatic discharge clamp circuit 208 responds to the electrostatic discharge earlier than the functional circuit in order to prevent the electrostatic discharge current from flowing to the functional circuit. If the trigger voltage Vt of the electrostatic discharge clamp circuit 208 is too high, the timing of enabling the electrostatic discharge clamp circuit 208 is too late. Under this circumstance, the efficacy of the electrostatic discharge clamp circuit 208 is largely impaired. Moreover, in response to the trigger voltage Vt of the electrostatic discharge clamp circuit 208, a snapback phenomenon occurs.
The holding voltage Vh denotes a snapback breakdown voltage of the semiconductor device. The holding voltage Vh should be higher than the voltage of the voltage source. If the holding voltage Vh is lower than the voltage of the voltage source Vdd, the semiconductor device is suffered from the snapback problem. Since the holding voltage Vh of the semiconductor device is maintained constant, if the voltage of the voltage source Vdd is higher than the holding voltage Vh, a leakage current is continuously generated and passes through the semiconductor device. Due to the occurrence of the leakage current, the semiconductor device is possibly burnt out to cause a transient latch-up problem. That is, for designing the electrostatic discharge clamp circuit 208, the holding voltage Vh should be higher than the voltage of the voltage source Vdd.
If the voltage of the electrostatic discharge exceeds the second-breakdown point, the ESD current is abruptly increased. The second-breakdown current It2 denotes the maximum allowable leakage current that can be withstood by the electrostatic discharge clamp circuit 208. Once the ESD current reaches the second-breakdown current It2, the leakage current drift is generated. Under this circumstance, the semiconductor devices within electrostatic discharge clamp circuit 208 will be burnt out.
That is, if the transient voltage resulting from the electrostatic discharge reaches the trigger voltage Vt, the electrostatic discharge clamp circuit 208 is enabled. Then, as the voltage is decreased, the relationship between the leakage current and the voltage pulls the voltage back to the holding voltage Vh. As the voltage is continuously changed, if the voltage reaches the second-breakdown current It2, it means that the electrostatic discharge clamp circuit 208 is burnt out.
From the above discussions, the characteristics of the trigger voltage Vt, the holding voltage Vh and the second-breakdown current It2 should be taken into consideration when designing the electrostatic discharge clamp circuit, so that the performance of the electrostatic discharge clamp circuit will be enhanced. Therefore, there is a need of providing an improved electrostatic discharge clamp circuit.